During a semiconductor fabrication process semiconductor dice are formed on a wafer. Subsequent to the fabrication process the dice must be tested to evaluate the electrical characteristics of the integrated circuits formed on the dice. Tests for gross functionality are typically performed at the wafer level by probe testing. Burn-in tests and full functionality tests are typically performed after the dice have been singulated.
If the dice are packaged in a conventional plastic or ceramic package, the package provides an external lead system for testing. If the dice are to remain in an unpackaged condition, temporary packages may be required to house a single die for testing and to certify the die as a known good die (KGD). Some types of packaged dice, such as chip scale packages, can also require temporary packages for testing. U.S. Pat. No. 5,519,332 to Wood et al. discloses a representative temporary package for testing semiconductor dice.
One component of temporary packages for testing semiconductor dice functions as an electrical interconnect. The interconnect includes contact members for making temporary electrical connections with the dice. Typically, the contact members are configured to make electrical contact with corresponding contact locations on the dice, such as bond pads, test pads or fuse pads.
U.S. Pat. No. 5,483,741 to Akram et al. describes one type of interconnect for testing semiconductor dice. This type of interconnect includes a substrate, such as silicon, having integrally formed contact members. The contact members can be etched directly into the substrate and covered with a conductive layer. In addition, the interconnect includes conductors, such as deposited metal traces, for providing conductive paths to and from the contact members. One advantage of this type of interconnect is that the contact members can be formed in dense arrays using semiconductor fabrication processes. Since the contact members are formed integrally with the substrate, their location is fixed relative to the substrate and their CTE can match that of the substrate and a silicon die.
This type of interconnect functions satisfactorily for most types of testing. However, with advances in the architecture of semiconductor devices, it is advantageous to perform some testing of integrated circuits using very high speed testing signals. For example, testing frequencies of 500 MHz and greater are anticipated for some memory products such as DRAMS. The temporary packages and interconnects used to test dice must be capable of transmitting signals at these high speeds without generating parasitic inductance and cross coupling (i.e., “cross talk”).
One limitation of deposited metal conductors for interconnects is that the thickness of the metal conductors is limited by conventional deposition processes. Typically, CVD deposited metal conductors can be formed with a thickness of only about 2-3 μm. These thin conductors can be too resistive for high speed testing. The resistance can be lowered by widening the conductors but this greatly increases capacitance and causes speed delays.
Another limitation of deposited metal conductors for interconnects, is that low resistivity materials are sometimes difficult to utilize in conventional semiconductor fab shops. Copper, for example, is an unwanted contaminant for some semiconductor fabrication processes such as CVD and is preferable to avoid.
Another type of interconnect, as described in U.S. Pat. No. 5,487,999 to Farnworth, includes a rigid substrate such as silicon, but with contact members formed separately from the substrate. With this type of interconnect, the contact members can comprise metal microbumps mounted on a multi layered tape similar to TAB tape. The tape can also include conductors formed of copper foil or other highly conductive, relatively thick metal. The microbumps can be formed directly on the conductors or contained in vias formed in the tape.
Interconnects formed with microbump contact members and multi layered tape can include highly conductive conductors formed of copper foil or other relatively thick metal. However, during burn in testing temperature cycles of 200° C. or more can occur. The difference in the coefficients of thermal expansion (CTE) between the conductors and a substrate material such as silicon, can generate thermal stresses in the interconnect. In addition, thermal expansion can cause the conductors to shift relative to the substrate. If the contacts members are formed in direct contact with the conductors, movement of the conductors can displace the location of the contact members.
The present invention is directed to a hybrid interconnect having contact members formed integrally with the substrate but with conductors formed on a multi layered tape. The multi layered tape can be formed separately from the interconnect substrate and then bonded to the interconnect substrate with the conductors in electrical communication with the contact members. This allows low resistivity conductors to be used without requiring deposition of metals such as copper that can be detrimental to other semiconductor fabrication processes. In addition, with the present interconnect the location of the contact members can be fixed on the substrate while thermal stresses between the conductors and substrate can be absorbed by expansion joints.